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Udit Kumar, PhD
VLSI | 5G, TSN, AI | IITD | Author | 18 years experience | EdgeQ | Ex. Mentor, Synopsys, STM, DGB
About
Udit Kumar, PhD is a highly experienced VLSI professional with 15 years of experience in RTL design, CDC, and flow & methodology. He holds a PhD in Electrical Engineering from IIT Delhi, a PG Diploma in VLSI design from CDAC (Mumbai), and a B.Tech in Electrical, Electronics, and Communications Engineering from Motivational Pathway. Currently working as a Principal Engineer at EdgeQ Inc., Udit is responsible for developing 5G Base Station on-a-Chip and a software-defined 5G+AI platform. Udit is a continuous learner who believes in knowledge sharing and has good patience in learning new domains. He is a published author of two books: "The VLSI Handbook: Design Principles, Industry & Career Perspectives" and "Fundamentals of 5G: Emphasis on fronthaul and TSN protocols," available on Amazon Kindle. Udit is also a Knowledge Sharing Contributor at Learn VLSI, where he shares his expertise in the VLSI field to help people at an early stage of their career. Udit's expertise lies in developing IP from scratch, architecture, micro-architecture definition, RTL design, and static checks such as lint and Clock domain crossing. He has successfully developed (Idea to product) and silicon tested an adaptive router chip. He has good experience in 5G fronthaul protocols such as JESD204B/C, CPRI, Frame preemption, PTP, and Automotive Ethernet, TSN protocols Automotive PHY, gPTP, and Frame Preemption. Udit has good expertise in front-end flow & methodologies and has technically led projects and collaborated with global teams. In his previous role as Lead Member Consulting Staff at Mentor Graphics, Udit worked on the development of 5G IP and solutions. He led a team for the development of Automotive Ethernet specific IP from scratch and worked on various standard protocol IP's such as JESD204B, JESD204C, CPRI, Automotive PHY, Timing synchronization(gPTP), and Frame preemption. Udit was responsible for developing functional specification, microarchitecture, RTL, and Signoff checks. These IP are used in various product lines such as emulation, prototyping, and ICE. Udit's tech stack includes AI and Frontend, and he has relevant experience of 9.77 years. He is a hardworking individual who works positively to meet organizational goals.
Education Overview
• iit delhiindian institute of technology delhi
• cdac mumbai
• uptu
Companies Overview
• edgeq
• learn vlsi
• mentor graphics
• synopsys
• atrenta
• stmicroelectronics
• digibee microsystems
Experience Overview
12.1 Years
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Experience
Skills
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architecture
Artificial Intelligence (AI)
Automotive
Collaboration
Consulting
Design
Electrical Engineering
Ethernet
Frontend
IP
Prototyping
rtl design
Very-Large-Scale Integration (VLSI)
vlsi
Contact Details
Email (Verified)
udiXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXX95Education
iit delhiindian institute of technology delhi
Doctor of Philosophy (Ph.D.)
2009 - 2015
cdac mumbai
PG Diploma
2006 - 2006
uptu
Bachelor of Technology - BTech
2001 - 2005
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